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CMOS 8-Bit High Speed Analog-to-Digital Converter
April 2002
XRD8785
FEATURES * 8-Bit Resolution
* Up to 20 MHz Sampling Rate * Internal S/H Function * Single Supply: 5V * VIN DC Range: 0V to VDD * VREF DC Range: 1V to VDD * Low Power: 75mW typ. (excluding reference) * Latch-Up Free * ESD Protection: 2000V Minimum
* 20-Pin Package Available: XRD8775 * 3V Version: XRD87L85
APPLICATIONS * Digital Color Copiers
* Cellular Telephones * CCDs and Scanners * Video Capture Boards
GENERAL DESCRIPTION The XRD8785 is an 8-bit Analog-to-Digital Converter. Designed using an advanced 5V CMOS process, this part offers excellent performance, low power consumption, and latch-up free operation.
This device uses a two-step flash architecture to maintain low power consumption at high conversion rates. The input circuitry of the XRD8785 includes an on-chip S/H function which allows the user to digitize analog input signals between AGND and AVDD. Careful design and chip layout have achieved a low analog input capacitance. This reduces "kickback" and eases the requirements of the buffer/amplifier used to drive the XRD8785. The designer can choose the internally generated reference voltages by connecting VRB to
VRBS and VRT to VRTS, or provide external reference voltages to the VRB and VRT pins. The internal reference generates 0.6V at VRB and 2.6 V at VRT. Providing external reference voltages allows easy interface to any input signal range between AGND and AVDD. This also allows the system to adjust these voltages to cancel zero scale and full scale errors, or to change the input range as needed. The device operates from a single +5V supply. Power consumption is 75mW at FS = 15MHz. Specified for operation over the commercial/industrial (-40 to +85C) temperature range, the XRD8785 is available in Plastic Dual-in-line (PDIP), Surface Mount (SOIC) and Small Outline (SOP) packages in EIAJ and JEDEC.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
Rev. 3.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
XRD8785
ORDERING INFORMATION
Package Type SOIC (Jedec) SOP (EIAJ) Plastic Dip (300MIL) Temperature Range -40 to +85C -40 to +85C -40 to +85C Part No. XRD8785AID XRD8785AIK XRD8785AIP DNL (LSB) +/- 0.75 +/- 0.75 +/- 0.75 INL (LSB) +/-1.5 +/-1.5 +/-1.5
PIN CONFIGURATIONS See Packaging Section for Package Dimensions
24-Pin PDIP (300 MIL) - P24
24-Pin SOP (EIAJ, 5.4mm) - K24 24-Pin SOIC (Jedec, 300 MIL) - D24
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 NAME OE DGND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DVDD CLK DESCRIPTION Output Enable Digital Ground Data Output Bit 0 (LSB) Data Output Bit 1 Data Output Bit 2 Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 Data Output Bit 6 Data Output Bit 7 (MSB) Digital Power Supply Sampling Clock Input PIN NO. 13 14 15 16 17 18 19 20 21 22 23 24 NAME DVDD AVDD AVDD VRTS VRT AVDD VIN AGND AGND VRBS VRB DGND DESCRIPTION Digital Power Supply Analog Power Supply Analog Power Supply Generates 2.6 V if tied to VRT Top Reference Analog Power Supply Analog Input Analog Ground Analog Ground Generates 0.6 V if tied to VRB Bottom Reference Digital Ground
Rev. 3.00
2
XRD8785
ELECTRICAL CHARACTERISTICS TABLE UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 5V, FS = 15MHZ (50% DUTY CYCLE), VRT = 2.6V, VRB = 0.6V, TA = 25C
25C Parameter KEY FEATURES Resolution Sampling Rate ACCURACY Differential Non-Linearity Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage3 Ladder Resistance Ladder Temp. Coefficient Self Bias 1 Short VRB and VRBS Short VRT and VRTS Self Bias 2 VRB = AGND, Short VRT and VRTS ANALOG INPUT Input Bandwidth (-1 dB)2, 4 Input Voltage Range Input Capacitance Aperture Delay2 DIGITAL INPUTS Logical "1" Voltage Logical "0" Voltage DC Leakage Currents 6 CLK OE Input Capacitance Clock Timing ( See Figure 1.)7 Clock Period High Pulse Width Low Pulse Width DIGITAL OUTPUTS Logical "1" Voltage Logical "0" Voltage 3-state Leakage Data Valid Delay 8 Data Enable Delay Data 3-state Delay VOH VOL IOZ t DL tDEN tDHZ 10 10 5 5 4.5 0.4 V V 1/FS tPWH tPWL 50 25 25 66.7 33.3 33.3 ns ns ns C OUT =15 pF I LOAD = 4 mA I LOAD = 4 mA V OUT =DGND to DVDD VIH VIL IIN 5 5 5 4.0 1.0 V V VIN =DGND to DVDD
5
Symbol
Min 8
Typ
Max
Units Bits
Test Conditions/Comments
FS DNL DNL INL EZS EFS VRT VRB V REF RL RTCO VRB VRT-VRB VRT
0.1
15
20 +/-0.75
MHz LSB LSB LSB LSB LSB @ 15MHz @ 10MHz Best Fit Line (Max INL - Min INL)/2
+/-0.5 +/-1.5 +3 -2 2.6 AGND 1.0 245 350 2000 0.6 2 2.3 0.6 AVDD 550 AVDD
V V V VREF = VRT - VRB
ppm/C V V V
BW VIN CIN tAP VRB
50 VRT 16 3
MHz V pF ns
A A
pF
A
ns ns ns
Rev. 3.00
3
XRD8785
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 5V, FS = 15MHZ (50% DUTY CYCLE), VRT = 2.6V, VRB = 0.6V, TA = 25C
25C Parameter AC PARAMETERS Differential Gain Error Differential Phase Error POWER SUPPLIES Operating Voltage (AVDD, DVDD)9 Current (AGND + DGND) VDD I DD 4.5 5 15 5.5 25 V mA Does not include ref. current dg dph 2 1 % Degree FS = 4 x NTSC FS = 4 x NTSC Symbol Min Typ Max Units Test Conditions/Comments
NOTES 1. The difference between the measured and the ideal code width (VREF/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4). Accuracy is a function of the sampling rate (FS). 2. Guaranteed, not tested 3. Specified values guarantee functionality. Refer to other parameters for accuracy. 4. -1dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5. See VIN input equivalent circuit (Figure 5). Switched capacitor analog input requires driver with low output resistance. 6. All inputs have diodes to DVDD and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD . 7. tR , tF should be limited to >5ns for best results. 8. Depends on the RC load connected to the output pin. 9. AGND & DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3
VDD to GND .......................................................... 7V VRT & V RB ......................... VDD +0.5 to GND -0.5V VIN ..................................... VDD +0.5 to GND -0.5V All Inputs ............................ VDD +0.5 to GND -0.5V All Outputs ......................... VDD +0.5 to GND -0.5V Storage Temperature .........................-65 to +150C Lead Temperature (Soldering 10 seconds) ... +300C Package Power Dissipation Rating @ 75C PDIP, SOIC, SOP ................................. 675mW Derates above 75C ........................... 12mW/C
NOTES: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. 3. VDD refers to AVDD and DVDD. GND refers to AGND and DGND.
Rev. 3.00
4
XRD8785
Figure 1. XRD8785 Timing Diagram
Figure 2. Output Enable/Disable Timing Diagram
Figure 3. DNL Measurement
Figure 4. INL Error Calculation
Rev. 3.00
5
XRD8785
Figure 5. Equivalent Input Circuit
Figure 6. Typical Circuit Connections
APPLICATION NOTES Signals should not exceed VDD +0.5V or go below GND -0.5V. All pins have internal protection diodes that will protect them from short transients (<100s) outside the supply range. AGND and DGND pins are connected internally through the P-substrate. DC voltage differences between GND pins will cause undesirable internal substrate currents. The power supply (VDD) and reference voltage (VRT & VRB) pins should be decoupled with 0.1F and 10F capacitors to AGND, placed as close to the chip as possible. The digital outputs should not drive long wires or buses. The capacitive coupling and reflections will contribute noise to the conversion.
To avoid timing errors, use the rising edge of the sample clock (CLK) to latch data from the XRD8785 to other parts of the system. The reference can be biased internally by shorting VRT to VRTS and VRB to VRBS. This will generate 0.6V at VRB and 2.6V at VRT (see Figure 5). If the internal reference pins VRTS and/or VRBS are not used, they should be left unconnected. The output enable pin (OE) should not be left unconnected. If not controlled by an active signal then it must be tied to a logic low value.
Rev. 3.00
6
XRD8785
PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4 0.2 DNL (LSB) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 Code 160 192 224 256 Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Fs = 15MHz Ta = 25 oC
Graph 1. DNL vs. Code
1.0 0.8 0.6 0.4 0.2 INL (LSB) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 Code 160 192
Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Fs = 15MHz Ta = 25 oC
224
256
Graph 2. INL vs. Code
Rev. 3.00
7
XRD8785
1.0 0.8 0.6 0.4 0.2 DNL (LSB) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0.10 NEG DNL POS DNL Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Ta = 25 oC
1.00 Fs (MHz)
10.00
100.00
Graph 3. DNL vs. Sampling Frequency
1.0
Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Ta = 25 oC
0.8
0.6 INL (LSB) 0.4 0.2 0.0 0.10
1.00 Fs (MHz)
10.00
100.00
Graph 4. Best Fit INL vs. Sampling Frequency
Rev. 3.00
8
XRD8785
24 Ta = 25 oC
20
Vdd = 5.5V 16
Idd (mA)
Vdd = 5.0V 12
Vdd = 4.5V 8
4
0 0 5 10 15 Fs (MHz) 20 25 30
Graph 5. IDD vs. Sampling Frequency
20 18 16 14 Fs = 20MHz 12 Idd (mA) Fs = 15MHz 10 8 6 4 2 0 -60 -40 -20 0 20 Temperature (C) 40 60
Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V
Fs = 10MHz
80
100
Graph 6. Supply Current vs. Temperature
Rev. 3.00
9
XRD8785
550 Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V 500
Ladder Resistance (ohm)
450
400
350
300
250 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Graph 7. Ladder Resistance vs. Temperature
50 45 40 35 30
Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Fs = 15MHz Ta = 25oC
SNR (dB)
25 20 15 10 5 0 0.01
0.1
1
10
Fin (MHz)
Graph 8. SNR vs. Input Frequency
Rev. 3.00
10
XRD8785
50 45 40 35 30 SINAD (dB) 25 20 15 10 5 0 0.01 Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Fs = 15MHz o Ta = 25 C
0.1 Fin (MHz)
1
10
Graph 9. SINAD vs. Input Frequency
80 60 40 20 0 -20 -40 -60 -80 -100 -120 0.0 1.5 3.0 Freq (MHz) 4.5 6.0
Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Fs = 15MHz Fin = 500KHz
Amplitude (dB)
7.5
Graph 10. FFT Plot
Rev. 3.00
11
XRD8785
24 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
REV. 1.00
24 1 D
13 12 E1
E
Seating Plane
A L A1 B e B1
A2 C
eA eB
Note: The control dimension is the inch column
INCHES SYMBOL A A1 A2 B B1 C D E E1 MIN 0.145 0.015 0.115 0.014 0.030 0.008 1.125 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 1.275 0.325 0.280 0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 28.58 7.62 6.10 2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 5.08 15 MAX 5.33 1.78 4.95 0.56 1.78 0.38 32.39 8.26 7.11
e
eA eB L a
Rev. 3.00
12
XRD8785
24 LEAD EIAJ SMALL OUTLINE (5.4 mm EIAJ SOP)
REV. 1.00
D
24
13
E
1 12
H
C A2 Seating Plane e B A1 L A
INCHES SYMBOL A A1 A2 B C D E e H L a MIN 0.069 0.002 0.067 0.012 0.004 0.587 0.209 0.050 BSC 0.299 0.012 0 0.315 0.030 10 7.60 0.30 0 MAX 0.083 0.008 0.075 0.020 0.008 0.594 0.217 MIN 1.75 0.05 1.70 0.30 0.10
MILLIMETERS MAX 2.10 0.20 1.90 0.50 0.20 15.10 5.50 1.27 BSC 8.00 0.76 10
14.90 5.30
Rev. 3.00
13
XRD8785
24 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
REV. 1.00
D
24
13
E
1 12
H
C A Seating Plane e B A1 L
INCHES SYMBOL A A1 B C D E e H L a MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.419 0.050 8
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 1.27 BSC 10.00 0.40 0 10.65 1.27 8 MAX 2.65 0.30 0.51 0.32 15.60 7.60
0.050 BSC
Rev. 3.00
14
XRD8785
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2002 EXAR Corporation
Datasheet April 2002 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.00
15

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